This invention relates to methods of forming refractory metal silicide components and methods of restricting silicon surface migration of an etched silicon structure relative to a surface of an underlying refractory metal layer.
Fabrication of semiconductor devices involves forming electrical interconnections between electrical components on a wafer. Electrical components include transistors and other devices which can be fabricated on the wafer. One type of electrical interconnection comprises a conductive silicide line the advantages of which include higher conductivities and accordingly, lower resistivities.
Typically, conductive silicide components can be formed by blanket depositing a layer of refractory metal over the wafer and then blanket depositing a layer of silicon over the refractory metal layer. For example, referring to FIG. 1, an exemplary wafer fragment in process is shown generally at 10 and includes a substrate 12. Exemplary materials for substrate 12 comprise suitable semiconductive substrate materials and/or other insulative materials such as SiO2. As used is this document, the term xe2x80x9csemiconductive substratexe2x80x9d will be understood to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. A refractory metal layer 14 is formed over substrate 12 followed by formation of a layer 16 of silicon.
Referring to FIG. 2, layer 16 is patterned and etched to form a plurality of silicon-containing structures 17. Silicon-containing structures 17 constitute structures from which electrical interconnects are to be formed relative to wafer 10. The etching of the silicon-containing structures defines a silicon-containing structure dimension d1 and a silicon-containing structure separation distance d2. In the illustrated example, d1 is substantially equal to d2. Such relationship between d1 and d2 results from a desire to use as much of the wafer real estate as is available. Accordingly, the spacing between the silicon-containing structures reflects a critical dimension which is a function of the limitations defined by the photolithography technology available. The goal is to get the silicon-containing structures as close as possible to conserve wafer real estate.
Referring to FIG. 3, substrate 12 is exposed to suitable conditions to cause a reaction between the refractory metal layer 14 and the silicon-containing structures 17. Typical conditions include a high temperature annealing step conducted at a temperature of about 675xc2x0 C. for about 40 seconds. Subsequently, the unreacted refractory metal is stripped from the wafer. The resulting refractory metal silicide components or lines are illustrated at 18 where the resulting line dimensions d1xe2x80x2 can be seen to be larger than the silicon-containing structure dimensions d1 (FIG. 2) from which each was formed. Accordingly, the relative spacing or separation between the lines is illustrated at d2xe2x80x2. With the attendant widening of the silicide components or lines, the separation distance between them is correspondingly reduced. A major cause of this widening is the diffusive nature of the silicon from which the FIG. 2 silicon-containing structures are formed. That is, because silicon is highly diffusive in nature, the formation of the FIG. 3 silicide components causes a surface migration of the silicon relative to the underlying substrate. In the past, when device dimensions were larger, the migration of silicon during silicide formation was not a problem. Adequate spacing between the resulting silicide lines ensured that there would be much less chance of two or more components shorting together. However, as device dimensions grow smaller, particularly at the 0.35 xcexcm generation and beyond, there is an increased chance of shorting. This is effectively illustrated in FIG. 4 where two refractory metal components 19 can be seen to engage one another and hence short together at 20.
This invention grew out of concerns associated with forming silicide components. This invention also grew out of concerns associated with improving the integrity of electrical interconnections as device dimensions grow ever smaller.
Methods of forming refractory metal silicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restricting layer is formed over at least some of the silicon-containing structure. The substrate is subsequently annealed at a temperature which is sufficient to cause a reaction between at least some of the refractory metal layer and at least some of the silicon-containing structure to at least partially form a refractory metal silicide component. In accordance with one aspect of the invention, a silicon diffusion restricting layer is formed over or within the refractory metal layer in a step which is common with the forming of the silicon diffusion restricting layer over the silicon-containing structure. In a preferred implementation, the silicon diffusion restricting layers are formed by exposing the substrate to nitridizing conditions which are sufficient to form a nitride-containing layer over the silicon-containing structure, and a refractory metal nitride compound within the refractory metal layer. A preferred refractory metal is titanium.